The present invention relates to a read only memory using a nonvolatile memory device.
Read only memories using a nonvolatile memory device a floating gate structure as a memory cell can rewrite data. Therefore, such a memory is used in various systems including a microcomputer system. As is well known, the above nonvolatile memory device has two gates consisting of a floating gate and a control gate. When the electrons have been preliminarily injected into the floating gate, the threshold voltage is set to be high, so that even if a high level signal, e.g., +5 V, is applied to the control gate, the device will not be turned on. On the other hand, when no electron is injected in the floating gate, the threshold voltage is maintained to be inherently low, so that when a high level signal is applied to the control gate, the memory device will be turned on. In this way, in the memory using the nonvolatile memory device as the memory cell, data is stored by allowing the state in that when a high level signal was applied to the control gate of the memory device, the device is turned on or off to correspond to the "1" or " 0" level of the data.
In the following description, the state in which the threshold voltage became a high level is set into the memory state of "0" level data, while the state which is inherently maintained at a low level is set into the memory state of "1" level data.
In addition, to inject electrons in the floating gate of the memory device, a high potential, e.g., +20 to +25 V, which is much higher than +5V, is applied to both the control gate and drain. Due to this, the impact ionization occurs in the channel region near the drain, causing electron-hole pairs, so that the electrons among them are injected in the floating gate. Since the electrons injected in the floating gate remain (except in the case where data is erased), once the data which has been stored in the memory device, it is held to be nonvolatile.
In the memory using such a floating gate memory device as the memory cell, a sense amplifier of the differential type is used to reduce the quantity of data to be written in the memory cell and to raise the data readout speed. Such a memory provided with the sense amplifier is disclosed in, for instance, the drawing of U.S. Pat. No. 4,223,394. In the memory shown, a dummy memory device is provided corresponding to the memory device. No electrons are injected in the floating gate of this dummy memory device, and a lower potential than that to be applied to the control gate when the memory device was selected is always applied to the control gate. Due to this, the reference potential which was set into the intermediate potential of the potential amplitude which varies depending upon the readout data from the memory device is formed, and the signal potential in response to the readout data is compared with the reference potential by a differential amplifier, thereby sensing the data.
This conventional memory is designed in such a manner that the reference potential under the particular power potential becomes the intermediate potential of the signal potential amplitude. Due to this, in the case where the power potential changed, or in case of making the system operative at a power potential different from the design power potential, the reference potential will have deviated from the intermediate potential of the signal potential amplitude. Consequently, upon reading out the data at "1" or "0" level, either margin can deteriorate causing the wrong data to be sensed.